AMS SerDes Robustness Analysis & Validation Architect

Are you inherently curious, hands-on, and analytical? We are seeking a seasoned SerDes Robustness Analysis & Validation Architect with a strong technical foundation and a hands-on approach to drive the robustness, performance, and margin validation of high-speed SerDes PHYs, such PCIe and USB, within our system. This role is ideal for someone who is motivated to push designs to the edge through intentional stress testing and margin-finding techniques! You will architect validation strategies that go beyond traditional spec-checking, focusing on uncovering weaknesses in design assumptions, stress-to-fail conditions, and system interactions across wide-ranging PVT and real-world scenarios, including edge case behaviors. A deep understanding of SerDes design and validation principles, SOC/system integration, and real-world system environments is required. In addition, you will also partner closely with the validation team to help optimize for maximum test coverage vs. execution time, ensuring efficient yet thorough validation. This is a hands-on lab role that requires strong collaboration with designers, architects, system, and test engineers to validate next-generation SerDes IPs from design conception through production and to ensure the IP is designed with design for testability.